1. Field of the Invention
The present invention relates to a semiconductor apparatus testing arrangement and a semiconductor apparatus testing method, and, in particular, to a semiconductor apparatus testing arrangement and a semiconductor apparatus testing method by which a plurality of enhanced and/or high-speed-operation-type semiconductor devices produced on a single semiconductor substrate (wafer) can be tested simultaneously.
2. Description of the Related Art
Along with a demand for an enhanced and/or high performance electronic apparatus, a highly-integrated, high-speed or large-capacity semiconductor apparatus (LSI circuit) is demanded for mounting on the electronic apparatus.
For this purpose, in a semiconductor device (LSI chip) included in the semiconductor apparatus, the operation speed is increased, the number of external connection terminals is increased, and also, separations among the external connection terminals are reduced. Especially in a system LSI circuit, this tendency is remarkable, and thereby, testing of the system LSI circuit with high reliability may become difficult.
On the other hand, as a common issue of a corresponding industry, it is required to simultaneously test a plurality of semiconductor devices such as the system LSI chips each having many external connection terminals, in order to maintain productivity and reduce product the costs.
Especially, to carry out testing of a plurality of semiconductor devices each having many fine external connection terminals, simultaneously in a state in which these semiconductor devices are produced on a semiconductor substrate (wafer), with high testing accuracy (for electric characteristics and mechanical contact characteristics) is one of essential issues for satisfying a demand of the expanding semiconductor apparatus market.
A test system for testing semiconductor devices has, as a basic configuration, an LSI tester body and a testing substrate (probe card). The probe card includes an opening, probe needles arranged in the opening for contacting electrode terminals of a to-be-tested semiconductor device, tester pin connecting terminals arranged on the periphery of the testing substrate, electric wires connecting between the probe needles and the tester pin connecting terminals, a power source electric conductor, a ground electric conductor and so forth.
The probe needles contact the electrode terminals of the to-be-tested semiconductor device, and in this state, pins of the LSI tester body are connected with the tester pin connecting terminals of the probe card. Thus, electric connection between the semiconductor device and the LSI tester body is made, and the semiconductor device is tested.
A plurality of semiconductor devices produced on a semiconductor substrate are tested simultaneously in the prior art. For example, Japanese Laid-open Patent Applications Nos. 56-61136 and 9-172143 disclose that, to electrodes of two laterally, longitudinally or obliquely adjacent semiconductor chips, probe needles are made to contact, and these two semiconductor chips are tested simultaneously.
In a case where two laterally or longitudinally arranged semiconductor devices (semiconductor chips) are tested simultaneously, probe needles can be easily made to contact electrodes of the two semiconductor chips, and also, lengths of electric wires led from the probe needles can be made uniform, if a direction in which the electrode terminals are arranged and a direction in which the semiconductor chips are arranged can be made coincident, for example, a direction in which the electrode terminals are arranged in a common direction as in a semiconductor storage (memory device).
Japanese Laid-open Patent Applications Nos. 11-16963 and 57-183571 disclose a configuration of a probe card provided with four mutually apart contact needle groups, and disclose that, with the use of this probe card, four semiconductor chips, located on a semiconductor substrate, to be apart by a distance corresponding to a plurality of the semiconductor chips, are tested simultaneously.
When the above-mentioned testing system is applied to test enhanced and/or high-speed-operation-type semiconductor device, a basic requirement is to shorten a transmission distance between each channel (pin) terminal of the LSI tester which is a main testing apparatus and a respective one of electrode terminals of the to-be-tested semiconductor device, and to minimize difference in the distances of the transmission circuits among the respective electrode terminals of the to-be-tested semiconductor device. This is because, an impedance increases as the length of the transmission circuit increases, and electric response degrades accordingly. Also, if difference occurs in the transmission circuit distances (wiring lengths or probe needle lengths), electric signal transmission delay (skew) occurs, and thus, temporal difference occurs in input/output timing of electric signals among the respective terminals.
In order to optimize electric characteristics of the signal transmission circuits (minimize the distances and eliminate difference therebetween), electric wires of the probe card are distributed on peripheral four sides of the semiconductor device corresponding to an arrangement of the electrode terminals of the to-be-tested semiconductor device, and are connected to contact terminals (probe terminals), respectively. By this method, minimization and uniformization of the signal transmission paths may be achieved for the respective electrode terminals of the to-be-tested semiconductor device. For a case where the single semiconductor device is tested, this manner is advantageous.
However, for a case where a plurality of semiconductor devices produced on a common semiconductor substrate are tested simultaneously for the purpose of improving test efficiency, the above-described manner in the prior art may be difficult to be applied. In the arts disclosed by Japanese Laid-open Patent Applications Nos. 56-61136 and 9-172143, for a case where the electrode terminals are arranged on four sides of each to-be-tested semiconductor device, probe needles should extend across the semiconductor device for contacting electrode terminals disposed in a direction perpendicular to a direction where the semiconductor devices are arranged in the proximity to a boundary between the adjacent semiconductor devices. Accordingly, the length of the probe needles should be necessarily longer than those of the other probe needles.
Further, at the boundary portion of the adjacent semiconductor devices, the probe needles for the electrode terminals arranged in the direction perpendicular to the direction in which the semiconductor devices are arranged extend across the semiconductor device, and also, are led in the same direction, in parallel, and in close proximity to the probe needles contacting the opposite electrode terminals of the same to-be-tested semiconductor devices. Accordingly, a density of these probe needles increases at a position at which the probe needles are led out, which results in increase in stray capacitance between the probe needles. As a result, in such a probe needle arranging and leading manner, the above-mentioned requirements for low impedance and optimization (minimum and uniform distances) of the transmission circuits may be difficult to achieve.
The needles provided in the probe card may be made to simultaneously contact for two obliquely adjacent semiconductor chips from a corner of these semiconductor chips, for testing the two semiconductor chips. In this manner, probe needles can be prevented from extending across the semiconductor chips. However, also in this manner applied for the obliquely adjacent semiconductor chips, lengths of probe needles led from the four sides of the semiconductor device cannot be made uniform. Accordingly, this manner is not an ultimate solution either.
According to Japanese Laid-open Patent Application Nos. 11-16963 and 57-183571, four semiconductor devices (semiconductor chips) can be tested simultaneously. However, no specific plan is disclosed for a specific manner of leading electric wires from the four contact needle (probe needle) groups, drawing electric wires for the tester pin connecting terminals, and so forth. Also, no disclosure is made there for achieving simulations testing of a plurality of electric parts such as enhanced and/or high-speed-operation-type semiconductor devices.
Thus, in the prior arts, nothing is taught for simultaneously testing a plurality of semiconductor devices each having electrode terminals on four sides thereof provided on a common semiconductor substrate with signal transmission paths kept with low impedance and having substantially equal lengths, led from these to-be-tested semiconductor devices.